Synchronous systems usually use clock signals to operate various components of the circuit. Delays may occur during the transmission of the clock signals because the clock signals are usually distributed from the clock source to various locations within a circuit. Thus the clock delays and variations of these clock delays are to be considered when performing timing analysis to determine if a circuit can operate at a desired frequency. A clock tree can be used to route clock signals from a clock signal input at the root of the tree to “leaves” of the tree at different locations within the circuit.
Clock skew is caused by the unequal delay of the clock signals through different paths in the clock tree from the root to the leaves. A balanced clock tree can be used to reduce the difference in clock delays, and thus the skew between the clock signals distributed at the leaves of the tree can be reduced too. Clock skew can cause problems for both hold time and setup time constraints. When the hold time constraint is violated, the circuit operates incorrectly. When the setup time constraint is violated, the circuit may operate correctly if the clock frequency is reduced, but the performance of the circuit may be compromised.
There can be two types of skew in the clock at two leaves of the tree: known skew and unknown skew. If two paths through the tree use identical buffers and wires, then the delays along the paths will be matched, even if the delay itself cannot be predicted precisely, and the clock skew may be close to zero. Known skew is the skew introduced by the clock tree router due to layout constraints e.g., when paths are not identical. Analytical tools such as the SPICE open-source circuit simulator can be used to estimate the delay difference and thus the known clock skew between two leaves in the tree.
The second type of skew, the unknown skew, is caused by differences in delay in the clock wires caused by factors that may not be predicted, such as random process variations, temperature variations and voltage variations (hereinafter “PVT variation”). For example, some wires may be wider than other wires; threshold voltages may have small random variations, the supply voltage may vary across the chip based on IR drop or instantaneous current flow, and the temperature may be different at different locations because of differences in activity and loading. In addition, cross-talk between wires can also introduce delay variations.
Known skew may be compensated for when constructing the circuit, but it is difficult to evaluate and compensate for unknown skew. For example, timing analysis tools may build in margin for both hold and setup time constraints to account for unknown skew, and such skew may reduce the performance of the circuit. This performance loss is often called “clock loss” because it measures the amount of the clock period lost to margins that are included to compensate for unknown skew so as to meet hold and setup time constraints.
The size of the delay variation caused by PVT is generally related to the length of the delay path. Thus the variation in the clock skew between two leaves is related to the length of the path from the nearest branch point in the tree. The clock-distance between two registers can be the height of the smallest subtree containing the registers. Two registers may be physically close but far apart in terms of clock-distance, and it is the clock-distance that determines the clock loss incurred by a path between two registers. The unknown clock skew can be the greatest between registers in the two partitions created at the top of the tree, or can be the least between registers in neighboring partitions at the bottom of the tree. Thus the clock loss is the greatest for circuit paths that span the two partitions at the top of the tree, e.g., crossing the top-level partition that partitions the tree. Such a path incurs a performance loss that is the maximum clock loss of the clock tree.